|
|
 |
|  | LOOKING FOR THE SWEET SPOT | | | Vendors are offering recipes for building less-expensive ASICs, but what are the real trade-offs? | | | By Richard A. Quinnell | |
|
 The design challenge is as old as the electronics industry: how to differentiate your product while keeping costs to a minimum. For the last decade, the answer has been to create an ASIC that repaid its development cost by providing a rich mix of functions unmatched in off-the-shelf chips. But the cost of creating ASICs has skyrocketed, due to design and manufacturing complexity at .13 micron and below. One of the industry's answers is to embrace what's being called the "structured ASIC" approach, in which only part of the chip is customized. A residual effect: It also simplifies the design chain.
Traditional ASICs are simply becoming too expensive in time and dollars for many potential customers. "At .13 micron, the nonrecurring engineering [NRE] costs are approaching $10 million," says Jim Lipman, president of consulting firm SemiView. "A few years ago, it was more like $50,000 to $100,000. In addition, design times are 12 to 18 months, running the risk that by the time a chip is finished, it may be obsolete."
The impact of this rising cost and complexity is apparent in market statistics. According to research firm IC Insights, the total ASIC market has dropped from nearly $21 billion in 2000 to less than $13 billion in 2003. Part, but not all, of this decline was due to the economic downturn of 2001. The ASIC market declined 42 percent in 2001, compared to an IC industry-average decline of 33 percent. In 2002, while the IC industry grew slightly (2 percent), the ASIC market declined an additional 6 percent.
 This lackluster performance is caused in part by longer design times, which reduce revenue opportunities, and in part by a reduction in demand due to rising NRE costs. Designs based on standard cells, the most common ASIC approach, have dropped from 5,200 design starts in 1997 to 1,400 in 2003, IC Insights reports.
To stimulate the market for their services, ASIC vendors are developing design approaches that accelerate the design effort and lower costs for customers. They're trying several different approaches, and the structured ASIC approach is gaining ground the fastest. A variety of companies-including LSI Logic, NEC, AMI, Fujitsu, Lightspeed Semiconductor, and Faraday Technologies-have developed structured ASIC offerings.
Gate Array's Heir
In basic terms, a structured ASIC is much like the gate arrays that were developed in the 1980s. It is a device designed and fabricated by the vendor, containing blocks of circuitry but stopping short of being a complete design. The last several metal layers are left undefined, so customers can make the final connections that turn those blocks into a custom IC. The prefabricated wafer, called a master slice, can be manufactured in volume by the ASIC vendor and stockpiled for customer use, spreading most of the device's development cost across many customers and pooling their manufacturing runs to achieve greater economies of scale.
The initial target markets for structured ASICs have been those in which high performance is needed but in which production volumes are modest. Under these constraints, the cost of developing a traditional ASIC results in an uncomfortably high per-part cost, yet the alternative FPGA approach cannot offer the needed performance. Applications such as data communications, data storage, and networking fall into this category and are the targets for most master slice offerings from structured ASIC vendors.
Companies that develop structured ASICs claim that there are significant savings in time and money for their customers. Mark Nelson, marketing director for LSI Logic's RapidChip structured ASIC line, estimates that a customer's total development cost is 20 to 25 percent that of a standard-cell design and that time to market is cut by as much as 50 percent.
 Such claims are not hype, according to analysts and early users (because companies are only now beginning to use the technology, vendors were unable to supply any end-user customer references). Bryan Lewis, principal analyst at Gartner, notes that structured ASICs "offer dramatically reduced design costs, to a point where they can be cost-effective in applications that have only $1.5 million in device revenue per design." Ravi Thummarukudy, vice president of the IC solutions division at design services company GDA Technologies, notes that in the designs his company has undertaken, mask charges for a .13-micron standard-cell design have been more than $700,000, whereas a structured ASIC design of similar complexity had mask costs of less than $100,000. In addition, Thummarukudy says, the physical design stage of a cell-based ASIC typically takes three to four months, whereas a structured ASIC design takes two to three weeks.
The structured ASIC approach simplifies the design of a custom chip for the vendor as well as the customer. "Traditionally in cell-based design, we had to do a lot of back-end layout work for customers," says Phil LoPresti, general manager of NEC Electronics America's custom LSI business unit. "The layout and physical design stage is quite intensive, so we needed a strong physical design team. To do a lot of designs, we needed a lot of engineers." With the structured ASIC approach, many of the difficult tasks such as clock tree layout and scan test insertion need to be done only once, when creating the master slice, instead of for every customer design, LoPresti notes. Taking the master slice the final steps to a customer design is relatively simple, "so we can handle more designs with fewer resources," says LoPresti.
 |
|
| "Structured ASICs will be the mainstream of custom chip design." Mark Nelson, LSI Logic |
|
Because developing the master slice involves the most difficult and error-prone design tasks, the level of customer expertise needed drops as well. This is particularly true during the physical-layer design stage. "Understanding the back-end design of a .13-micron standard cell ASIC is like sitting in a physics class," says GDA's Thummarukudy. "There are many details designers need to understand about device physics to make sure their designs will work." He notes that structured ASICs have already solved overall challenges such as power and ground distribution and addressed details such as electron migration, so his designers don't need to deal specifically with the device physics. "We can focus on functionality and timing closure," he says.
The reduction in customers' needs for design talent also show up in a reduction in the cost and complexity of design tools. Thummarukudy notes that the savings occur mostly in the middle and back-end design stages. "Design capture and logic verification are pretty much the same. What changes is synthesis and physical layout," he says. Because the transistor layout is already set in a structured ASIC, he adds, the physical design becomes a simple place-and-route. "You don't even need to worry about design-for-test; that's already built in," Thummarukudy adds.
Making the Right Slice
 All these benefits are available only if the master slice meets the customer's needs, so developing the right slice is crucial to success. "You have to find the right device," says GDA's Thummarukudy. "Does it have all the I/O you need, the RAM, the gates?" The device that meets your needs may also be overkill. "These are predetermined devices. You pay for the extra die size when there are elements you do not use," he adds. "The question is, Does that compromise outweigh the other benefits?"
Vendors use a variety of methods to arrive at a master slice design they believe minimizes the compromise for their target applications. In some cases, the ASIC vendor defines the master slice, based on its past experience with customers having similar needs. In cases in which the design chain becomes more crucial, the vendor works with a key customer to define the right slice for a target market. "As much as we ASIC vendors like to believe we know what a master slice should have, that knowledge is really only in our customers' heads," says Charlie Cheng, president of ASIC vendor Faraday Technology USA. "You have to partner with a leading customer to create the platform."
As an example, Cheng points to his company's experience with a master slice intended for consumer applications. "We created a superset of everything a consumer device might need," says Cheng. As a result, the master slice was too expensive to use in production in the price-sensitive consumer market. On the other hand, an LCD controller master slice Faraday developed with a key customer was highly successful. "It would have needed six or more ASICs to control all the different displays it used in its designs," Cheng notes. Working with Faraday allowed the customer to define a master slice from which it could quickly develop ASICs for each of the displays. That master slice now solves similar problems for many other customers.
The creation of such well-received master slices may have a significant impact on the electronics industry. Part of that impact is a boost in ASIC usage. Market research firm iSuppli expects that design starts and revenues from structured ASICs will grow significantly (see the chart "The Forecast for Structured ASICs"). Estimates from Dataquest and IC Insights are even more optimistic. Dataquest expects 200 structured ASIC design starts in 2004, growing to nearly 1,000 in 2007. IC Insights puts the 2008 sales of structured ASICs at more than 30 percent of an expected $12 billion in revenues from cell-based ASICs. Given the lower price of a structured ASIC, that 30 percent revenue share means that more than half of design starts will be structured ASICs.
 Design Chain Shifts
In addition to increasing ASIC design starts, structured ASICs will have an impact on the industry by altering the design chain for custom ICs. Currently, EDA companies develop tools for general-purpose IC development based on design rules. This leaves ASIC customers with a need to work closely with silicon vendors to resolve physical-layer design implementation details such as crosstalk and IR drop in power distribution. Structured ASICs shift the levels of effort around, giving ASIC customers a simpler design effort and making EDA companies work closely with silicon vendors.
"The amount of interaction required between customers and our design center decreases," says LSI Logic's Nelson. "There is more autonomy for customers, in that they can take their design closer to completion without help." By fixing many design details ahead of time, structured ASICs help eliminate the iterations between LSI Logic layout teams and its customers that were typically required in cell-based design efforts to resolve congestion and timing closure problems, Nelson adds.
The link between ASIC vendor and customer becomes so loose that some vendors are able to certify third-party design service companies to handle structured ASIC customers that do not have any ASIC design capability. "Lots of potential customers downsized their engineering staff during the last few years," says NEC's LoPresti, "and they are hesitant to hire more people now." Design service companies fill that gap, and vendor certification assures both design customers and ASIC vendors that the service provider can successfully create ASIC-based designs.
 Certified design service companies give silicon vendors access to more customers and serve as a supplementary sales force, with relatively little effort by the vendors. "We train them in how to complete a design with our structured ASICs and maybe work with them through their first design, and they come up to speed fairly quickly. In a month or two, they can be up and running," says LoPresti. NEC already works with the certified design companies GDA Technologies and CoreSim and expects to add as many as five more by midyear. Similarly, LSI Logic works with several certified third-party design companies, including Mint Technology and the design divisions of distributors Avnet, Arrow, and Memec.
The ongoing interaction with certified design service companies, as with customers, is minimal. "We do some monitoring and benchmarking of their ability to successfully hand off designs," says LoPresti. "We also have checks and balances for their design submissions, to make sure the customer is successful." LoPresti expects the design companies to need little, if any, ongoing support from NEC, although they will have access to on-call support and library updates.
Where customer interaction lessens, however, the ASIC vendor's interaction with the EDA tool provider increases, at least temporarily. "Cell-based synthesis tools didn't need to know about the target up front," says LSI Logic's Nelson, "so they could be more generic. Now there is more of a tightly coupled synergy between the silicon and tool providers. We have to make sure the tools for our customers work with the silicon design." However, once tuned to a master slice, Nelson expects, the tools will be relatively easy to adapt to new structured offerings. The ultimate result is a loosening of the ASIC design chain, easing the tool and silicon vendors' tasks, along with those of the design customers.
Challenges Remain
For all its appeal, the structured ASIC approach does have some remaining challenges. "There are two critical business chain breakdowns in the use of structured ASICs," says Faraday's Cheng. The first, he says, has to do with licensing fees. "Today's designs use a lot of licensed intellectual property," says Cheng, "and the basic question is: How do you determine the licensing fees for a design? If we put an ARM processor onto our master slice and sell it to 10 customers, is that one design or 10?" Cheng sees the potential for "a lot of legal wrangling" between ASIC vendors and IP providers.
The second breakdown comes in the manufacturing of the customer's final design. The master slice is prefabricated except for the last few metal layers. To finish the customer's design, the wafer must be reinserted into the foundry's processing flow for the final manufacturing steps. That causes a disconnect between the front-end and back-end manufacturing efforts. "Foundries do not like to interrupt their process flow for other wafers just to add metal to ours," says Cheng, "so there can be production delays if the foundry cannot schedule the wafer into the back-end flow in a timely manner." Such delays reduce the promised benefits of the structured ASIC approach.
Further, the structured ASIC approach is not right for every application. "If your design doesn't fit into an available master slice or you need a special interface that is not offered, you have no choice," says GDA's Thummarukudy. He also points out that a structured ASIC may not be cost-effective at high production volumes. "When you get to 10,000 to 50,000 units a year," Thummarukudy says, "standard-cell design may make better sense."Even so, the benefits remain compelling for many applications when structured ASICs offer the right mix of design elements. The fixed cost drops, design efforts are faster and easier, and devices reach production more quickly. Proponents expect that these benefits will ultimately change the way most development teams handle their custom chip design. "As we move forward," predicts Nelson, "structured ASICs will be the mainstream of custom chip design."
|
|
ABOUT THE AUTHOR |
|
 |
|
Richard A. Quinnell (rquinnell@designchain.comm) is a regular
contributor to EDC and a technology journalist who has been covering the electronics industry for more than 15 years. His background includes staff positions at EDN, Computer Design, and Silicon Strategies magazines. His work has also appeared in Electronic Business and Test and Measurement World |
|
Back to the top
|
|
