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 Transitions from one geometry to another, such as from 0.18 microns to 0.13 microns and 0.13 microns to 90 nanometers, are always difficult. The problem is that it's difficult to anticipate new factors that will need to be addressed. For example, the transition from 0.18 microns to 0.13 microns brought problems with 300-mm wafers, low-k dielectric technology, and the increased impact of interconnect parasitics, among other things.
 For the transition to 90-nm geometries, low-k is already being used, and 300-mm wafers are being processed. The expectation was that a seamless transition would occur and that wafer volumes would ramp up rapidly, but a range of unexpected problems arose at 90 nm. For example, 90-nm product yields are lower than expected and gate utilization is low as well, which means that the cost per gate is higher than with 0.13-micron technology. The performance of 90-nm chips continues to be lower than expected, and manufacturers that were expecting 90-nm chips to require less power have had to contend with leakage problems. As a result, the ramp-up of 90-nm wafer volumes is occurring more slowly than expected (see the "90-nm Wafer Volume Ramp-up" chart).
Many of the yield problems at 90 nm are related to design (leakage and interconnect tolerances) and influence product life-cycle costs, revenues, and profits (see the "Yield Factors" chart).
Most of the problems are in the following categories:
- Defect-density-related yield factors are relatively well controlled, although vias continue to be a problem;
- Lithography-based yield factors are tied into reticle patterns;
- Design- or circuit-related yield areas are the major contributors to yield losses, especially for designs that are performance-driven.
The circuit-related areas resonate with designers, because they relate to process tolerances and the impact on chip performance, which needs to be factored into the design tolerances. The process parameters that need tight control include leakage variations and interconnects, including via variations (multiple and redundant vias are being used). Unfortunately, the IC industry has underestimated the impact of the circuit-related factors on yields at 90 nm, and as a result, 90-nm wafer volumes continue to be very low.
Steps to take
To address the yield-related problems at 90 nm, the industry must utilize the experience base that has been built up by the early adopters, which has included increasing chip area (which can reduce interconnect congestion), reducing performance, increasing operating voltages (which can increase power), and removing mixed-signal functions. There is also the approach of changing architectures, such as using multiprocessors, as Apple is doing with its new systems, which use dual cores (the penalty is that this may require additional memory and more powerful compilers). There is, however, the need for IC vendors to link the design factors into product life-cycle costs and build the appropriate checks into the design steps to optimize manufacturing yields.
For the migration to 90 nm to support high-volume designs, yield consistency needs to be high, especially at the performance targets of the system. If there is 50 percent yield at 500 MHz but only 2 percent yield at 600 MHz and the customer needs 600 MHz, the payback for the design can be low. Unfortunately, the compromises that have to be made to generate high and consistent yields at 90 nm currently make the transition to this technology node unattractive for the mainstream IC market. Anytime there are problems, there are opportunities for the companies that have innovative solutions.
Design ramifications
Companies are being forced to change their approaches to design, to ensure that design-for-manufacturability and design-for-yield disciplines are included within the design phase. More simulation will be necessary at the system level, where there is in-depth understanding of the process tolerances. Design engineers need to consider strategies for optimizing yields and performance and maximizing chip area—that is, understanding the multiple dimensions involved in trade-offs. It is possible to have a respin of a design, but with reticle costs at 90 nm ranging from $1.2 million to $1.5 million, respin costs can be financially punishing. There is also the increased time to market for new designs.
There are major opportunities for new concepts in DFM and DFY. Smaller companies are offering some innovative concepts, but these capabilities need to be brought into the mainstream of the design space, which involves extensive marketing efforts. There will likely be a lot more simulation at the full-chip level, with allowances for the extremes of process variations. The verification tasks are compute- and engineering-intensive, and companies need to link the design intent with physical implementation.
The opportunities for innovation are excellent, but the IC industry needs to collaborate closely with the EDA industry on the solutions. If it can't transition rapidly to new generations of process technology, growth within the IC industry will slow, and that would be bad news for everyone in the electronics industry. |
